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Integrated Circuit Systems, Inc.
ICS843021
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
FEATURES
* 1 differential 3.3V LVPECL output * Crystal oscillator interface designed for 22.4MHz - 28MHz, 18pF parallel resonant crystal * Output frequency range: 112MHz - 140MHz * VCO range: 560MHz to 700MHz * Output duty cycle range: 49% - 51% * RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.37ps (typical) * RMS phase noise at 125MHz (typical) Offset Noise Power 100Hz ............... -94.2 dBc/Hz 1KHz .............. -122.8 dBc/Hz 10KHz .............. -132.2 dBc/Hz 100KHz .............. -131.3 dBc/Hz * 3.3V operating supply * 0C to 70C ambient operating temperature * Industrial temperature information available upon request * Lead-Free package fully RoHS compliant
GENERAL DESCRIPTION
The ICS843021 is a Gigabit Ethernet Clock Generator and a member of the HiPerClocksTM HiPerClockSTM family of high performance devices from ICS. The ICS843021 uses a 25MHz crystal to synthesize 125MHz. The ICS843021 has excellent phase jitter performance, over the 1.875MHz - 20MHz integration range. The ICS843021 is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space.
ICS
FREQUENCY TABLE - TYPICAL APPLICATIONS
Inputs Crystal Frequency (MHz) 25 26.6 Output Frequency (MHz) 12 5 133
BLOCK DIAGRAM
25MHz XTAL_IN
PIN ASSIGNMENT
VCCA VEE XTAL_OUT XTAL_IN 1 2 3 4 8 7 6 5 VCC Q0 nQ0 nc
OSC
XTAL_OUT
Phase Detector
VCO
/5
nQ0 Q0
ICS843021
/25 (fixed)
8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View
843021AG
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Integrated Circuit Systems, Inc.
ICS843021
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
Type Power Power Input Description Analog supply pin. Negative supply pin. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. No connect. Differential clock outputs. LVPECL interface levels. Core supply pin.
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3, 4 5 6, 7 8 Name VCCA VEE XTAL_OUT, XTAL_IN nc nQ0, Q0 VCC
Unused Output Power
TABLE 2. PIN CHARACTERISTICS
Symbol CIN Parameter Input Capacitance Test Conditions Minimum Typical 4 Maximum Units pF
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Integrated Circuit Systems, Inc.
ICS843021
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
4.6V -0.5V to VCC + 0.5V 50mA 100mA 101.7C/W (0 mps) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V10%, TA=0C TO 70C
Symbol VCC VCCA IEE Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Test Conditions Minimum 2.97 2.97 Typical 3.3 3.3 Maximum 3.63 3.63 85 Units V V mA
TABLE 3B. LVPECL DC CHARACTERISTICS, VCC = 3.3V10%, TA=0C TO 70C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCC - 1.4 VCC - 2.0 0.6 Typical Maximum VCC - 0.9 VCC - 1.7 1.0 Units V V V
NOTE 1: Outputs terminated with 50 to VCC - 2V.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency; NOTE 1 Equivalent Series Resistance (ESR) Shunt Capacitance NOTE 1: Input frequency is limited to a range of 22.4MHz - 28MHz due to VCO range. 14 Test Conditions Minimum Typical Fundamental 40 50 7 MHz pF Maximum Units
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V10%, TA=0C TO 70C
Symbol fOUT Parameter Output Frequency RMS Phase Jitter, (Random); NOTE 1 Output Rise/Fall Time Test Conditions 125MHz (Intergration Range: 1.875MHz to 20MHz) 20% to 80% Minimum 112 0.37 250 49 550 51 Typical Maximum 140 Units MHz ps ps %
tjit(O)
tR / tF
odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plot.
843021AG
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Integrated Circuit Systems, Inc.
ICS843021
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
TYPICAL PHASE NOISE AT 125MHZ
0 -10 -20 -30 -40 -50 -60 -70
10 Gb Ethernet Filter
125MHz
RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.37ps (typical)
NOISE POWER dBc Hz
-80 -90 -100 -110
Raw Phase Noise Data
-120 -130 -140 -150 -160
Phase Noise Result by adding a 10 Gb Ethernet Filter to raw data
100 1k 10k 100k 1M 10M 100M
-170 -180 -190
OFFSET FREQUENCY (HZ)
843021AG
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Integrated Circuit Systems, Inc.
ICS843021
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
2V
Phase Noise Plot
Noise Power
V CC
Qx
SCOPE
LVPECL
nQx
Phase Noise Mask
VEE
f1 Offset Frequency f2
-1.3V 0.33V
RMS Jitter = Area Under the Masked Phase Noise Plot
3.3V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
nQ0 Q0
Pulse Width t
PERIOD
80% Clock Outputs
80% VSW I N G
20% tR tF
20%
odc =
t PW t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
843021AG
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Integrated Circuit Systems, Inc.
ICS843021
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843021 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, and VCCA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin.
3.3V VCC .01F 10
V CCA .01F 10F
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS843021 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts.
XTAL_OUT C1 33p X1 18pF Parallel Crystal XTAL_IN C2 27p
Figure 2. CRYSTAL INPUt INTERFACE
843021AG
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Integrated Circuit Systems, Inc.
ICS843021
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
output frequency. The C1 = 27pF and C2 = 33pF are recommended for frequency accuracy. For different board layout, the C1 and C2 values may be slightly adjusted for optimizing frequency accuracy.
APPLICATION SCHEMATIC
Figure 3A shows a schematic example of the ICS843021. An example of LVEPCL termination is shown in this schematic. Additional LVPECL termination approaches are shown in the LVPECL Termination Application Note. In this example, an 18pF parallel resonant 25MHz crystal is used for generating 125MHz
VCC R2 10
VCCA VCC C3 10uF C4 0.01u U1 Q 1 2 3 4 VCCA VEE XTAL_OUT XTAL_IN VCC Q0 nQ0 NC 8 7 6 5 VCC + Zo = 50 Ohm
R3 133
R5 133
C2 33pF
25MHz 18pF
Zo = 50 Ohm nQ
X1
-
ICS843021 ICS843011
C5 0.1u R4 82.5 R6 82.5
C1 27pF
VCC=3.3V
FIGURE 3A. ICS843021 SCHEMATIC EXAMPLE
PC BOARD LAYOUT EXAMPLE
Figure 3B shows an example of ICS843021 P.C. board layout. The crystal X1 footprint shown in this example allows installation of either surface mount HC49S or through-hole HC49 package. The footprints of other components in this example are listed
in the Table 6. There should be at least one decoupling capacitor per power pin. The decoupling capacitors should be located as close as possible to the power pins. The layout assumes that the board has clean analog power ground plane.
TABLE 6. FOOTPRINT TABLE
Reference C1, C2 C3 C4, C5 Size 0402 0805 0603
R2 0603 NOTE: Table 6, lists component sizes shown in this layout example.
FIGURE 3B. ICS843021 PC BOARD LAYOUT EXAMPLE
843021AG
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Integrated Circuit Systems, Inc.
ICS843021
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843021. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS843021 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 10% = 3.63V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.63V * 85mA = 308.6mW Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.63V, with all outputs switching) = 308.6mW + 30mW = 338.6mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.339W * 90.5C/W = 100.7C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA
FOR
8-PIN TSSOP, FORCED CONVECTION
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 101.7C/W
1
90.5C/W
2.5
89.8C/W
NOTE: Most modern PCB designs use multi-layered boards.
843021AG
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3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 3.
VCC
ICS843021
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
Q1
VOUT RL 50 VCC - 2V
FIGURE 3. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = V (V
CCO_MAX
OH_MAX
=V
CC_MAX
- 0.9V
-V
OH_MAX
) = 0.9V =V - 1.7V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CC_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V
OH_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OH_MAX
) = [(2V - (V
CC_MAX
-V
OH_MAX
))/R ] * (V
L
CC_MAX
-V
OH_MAX
)=
[(2V - 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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Integrated Circuit Systems, Inc.
ICS843021
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 101.7C/W
1
90.5C/W
2.5
89.8C/W
TRANSISTOR COUNT
The transistor count for ICS843021 is: 1928
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Integrated Circuit Systems, Inc.
ICS843021
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
8 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 8. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 2.90 6.40 BASIC 4.50 Millimeters Minimum 8 1.20 0.15 1.05 0.30 0.20 3.10 Maximum
Reference Document: JEDEC Publication 95, MO-153
843021AG
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Integrated Circuit Systems, Inc.
ICS843021
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
Marking 3021A 3021A 021AL 021AL Package 8 lead TSSOP 8 lead TSSOP 8 lead "Lead-Free" TSSOP 8 lead "Lead-Free" TSSOP Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS843021AG ICS843021AGT ICS843021AGLF ICS843021AGLFT
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockSTM and FemtoClocksTM are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843021AG
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ICS843021
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
REVISION HISTORY SHEET
Rev
Table
Page 1 3 3 12 3 3 8 10 12 1 12
B
T4 T5
B C
T9 T3A
C
T6 T7 T9 T9
C
Description of Change Added Function Table. Features section - updated Cr ystal, Output Frequency & VCO range bullets. Cr ystal Characteristics Table - changed Frequency from 25MHz typical to 14MHz min. and 40MHz max. Added Note 1. AC Characteristics Table - changed Output Frequency from 125MHz typical to 112MHz min. and 140MHz max. Ordering Information Table - corrected count from 154 per tube to 100 Power Supply Table - increased VCC to 3.3V 10% from 5% and is reflected throughout the datasheet. Absolute Maximum Ratings - corrected Package Thermal Impedance air flow. Thermal Resistance Table - corrected air flow. Corrected air flow in table. Ordering Information Table - corrected marking. Features Section - added Lead-Free bullet. Ordering Information Table - added Lead-Free par t number.
Date
10/6/04
10/15/04 11/3/04
11/30/04
3/31/05
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